Imaging devices such as complementary metal oxide semiconductor (CMOS) imagers are commonly used in photo-imaging applications. A typical CMOS imager circuit includes a focal plane array of pixel cells. Each one of the cells includes a photoconversion device or photosensor such as, for example, a photogate, photoconductor, or photodiode, for generating and accumulating photo-generated charge in a portion of the substrate of the array. A readout circuit is connected to each pixel cell and includes at least an output transistor, which receives photo-generated charges from a doped diffusion region and produces an output signal that is read-out through a pixel access transistor.
One typical CMOS imager pixel circuit, the three-transistor (3T) pixel, contains a photosensor for supplying photo-generated charge to a diffusion region; a reset transistor for resetting the diffusion region; a source follower transistor having a gate connected to the diffusion region, for producing an output signal; and a row select transistor for selectively connecting the source follower transistor to a column line of a pixel array. Another typical CMOS imager pixel employs a four-transistor (4T) configuration, which is similar to the 3T configuration, but utilizes a transfer transistor to gate charges from the photosensor to the diffusion region and the source follower transistor for output.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, all of which are assigned to Micron Technology, Inc. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
FIG. 1 illustrates a typical four transistor pixel 50 utilized in CMOS imagers. The pixel 50 includes a photosensor 52 (e.g., photodiode, photogate, etc.), floating diffusion node N, transfer transistor 54, reset transistor 56, source follower transistor 58 and row select transistor 60. The photosensor 52 is connected to the floating diffusion node N by the transfer transistor 54 when the transfer transistor 54 is activated by a control signal TX. The reset transistor 56 is connected between the floating diffusion node N and an array pixel supply voltage. A reset control signal RESET is used to activate the reset transistor 56, which resets the photosensor 52 and floating diffusion node N as is known in the art.
The source follower transistor 58 has its gate connected to the floating diffusion node N and is connected between the array pixel supply voltage and the row select transistor 60. The source follower transistor 58 converts the stored charge at the floating diffusion node N into an electrical output voltage signal. The row select transistor 60 is controllable by a row select signal ROW SELECT for selectively connecting the source follower transistor 58 and its output voltage signal to a column line 62 of a pixel array.
FIG. 2 shows an exemplary CMOS imager circuit 200 that includes an array 230 of pixels (such as the pixel 50 illustrated in FIG. 1) and a timing and control circuit 232. The timing and control circuit 232 provides timing and control signals for enabling the reading out of signals from pixels of the array 230 in a manner commonly known to those skilled in the art. Exemplary arrays 230 have dimensions of M rows by N columns of pixels, with the size of the array 230 depending on a particular application.
Signals from the imager 200 are typically read out a row at a time using a column parallel readout architecture. The timing and control circuit 232 selects a particular row of pixels in the array 230 by controlling the operation of a row or vertical addressing circuit 234 and row drivers 240. Signals stored in the selected row of pixels are provided on the column lines 62 (FIG. 1) to a readout circuit 242 in the manner described above. The signal read from each of the columns is then read out sequentially using a horizontal/column addressing circuit 244. Differential pixel signals (Vrst, Vsig) corresponding to the read out reset signal and integrated pixel charge signal are provided as respective outputs Vout1, Vout2 of the readout circuit 242.
FIG. 3 more closely shows the rows and columns 349 of a typical CMOS imager 300. Each column 349 includes multiple rows of pixels 350 (such as the pixel 50 illustrated in FIG. 1). Pixel and reset signals from the pixels sensors 350 in a particular column can be read out to a readout circuit 352 associated with that column. The readout circuit 352 includes sample and hold circuitry for acquiring the pixel and reset signals. Signals stored in the readout circuits 352 are sequentially readout column-by-column onto lines 370, 372 to an output stage 354, which in the illustrated example is common to the entire array of pixels 330. The analog output signals Vout1, Vout2 may then be output, for example, to a differential analog circuit that subtracts the reset and pixel signals and sends them to an analog-to-digital converter (ADC). Alternatively, the reset and pixel signals may each be supplied to the analog-to-digital converter.
As can be seen from FIGS. 1-3, the CMOS image sensor chip normally integrates analog and digital components. As such, the analog circuitry inevitably suffers from substrate noise coupling. This is undesirable because substrate noise can compromise the signal-to-noise ratio of the imager. Substrate noise typically occurs when several circuits share the same substrate and large transient currents from some of the circuits are injected locally into the substrate through ohmic or capacitive coupling.
Differential readout, i.e., taking the difference of separately readout reset and pixel signals, is one way to reject common-mode substrate noise. In theory, any noise affecting the signals will be canceled when the signals are subtracted. Practically, however, since the reset and pixel signals are read out at different times, the noise may be different at those times. As such, the imager may still suffer from substrate noise.
One way of dealing with substrate noise is to use a dummy circuit, similar to a pixel circuit, located near the pixel circuit, but shielded from light as a reference signal source. Theoretically, the pixel and dummy circuit would see the same substrate noise, which can then be correlated by further processing. Unfortunately, the dummy circuit will cause a decreased fill factor (i.e., the ratio of light-sensitive pixel area to total pixel area) for the pixels, and for some architectures will cause an increase in KTC (thermal) noise.
Other proposed solutions include the use of complicated column and/or readout circuitry, which are also undesirable. Accordingly, there is a desire and need for an imager pixel circuit that does not suffer from substrate and other common-mode noise during a pixel readout operation, yet does not have increased complexity or fill factor.